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Cell controller ASIC

Residing on the cell board, the cell controller ASIC is part of the Integrity Superdome chipset. It coordinates traffic between the major components of a cell board and determines if a request requires communication with another cell or with the I/O subsystem. HP believes that this cell controller ASIC is the largest ASIC in the world—it has approximately 41 million transistors.

The cell controller ASIC has five major interfaces:

  • 4 memory subsystems

  • 2 ports to processors (1 dedicated port per 2 processors)

  • Crossbar interface, through which all communication to other cells flows

  • Processor-dependent hardware (PDH)

  • I/O interface, which connects the cell to an I/O subsystem

In addition to providing the interface logic, the cell controller ASIC maintains cache coherency throughout the system. The cell controller ASIC supports both Intel Itanium 2 and PA-8800 processors as well as the mx2 Dual-Processor Module.

The processor-dependent hardware (PDH) is the module that provides the cell with the local resources required to reset a cell and bring it up to a point where it can join other cells and boot the operating system. PDH contains the system boot firmware, which is also used at run time.

Memory controller ASIC

The memory controller ASIC is also part of the sx1000 Chipset. Its primary function is to multiplex and demultiplex data between the cell controller ASIC and the SDRAM in the memory subsystem. When the cell controller ASIC issues a read transaction on the memory interface command bus, the memory controller ASIC buffers the DRAM read data and returns it as soon as possible. When the cell controller ASIC issues a write transaction, the memory controller ASIC receives the write data from the cell controller ASIC and forwards it to the DRAM.

Note that only the data portion of the memory subsystem goes through the memory controller ASIC. All address and control signals to the DIMMs are generated by the cell controller ASIC and sent directly to the DIMM via the memory interface address bus.

The memory subsystem is a quad-ported implementation. It supports memory DRAM fault tolerance, in which a discrete SDRAM chip can fail without compromising data integrity. The memory subsystem provides 16 GB/s of peak bandwidth to the cell controller ASIC and reduces the overhead typically associated with directory coherency. What’s more, the memory subsystem enjoys a very low latency for cell-to-local-memory access: as low as 245 ns average idle load-to-use latency.

HP innovation with the new mx2 Dual-Processor Module

The recently introduced mx2 Dual-Processor Module provides HP Integrity server customers with a unique scalability and performance density option in addition to the traditional single Intel Itanium 2 processors. Now customers will have the choice of plugging a dual-chip module into the exact same socket used for single processors, providing up to double the number of processors and the performance density of the system.

The power of the mx2 Dual-Processor Module comes from two Intel Itanium 2 processors running at 1.1 GHz. They run at a reduced clock speed to limit power consumption and heat production. The mx2 Dual-Processor Module is powered by a single voltage regulator module (VRM). The mx2 Dual- Processor Module contains a bus converter and cache controller chip that enables the daughterboard to work with the rest of the system. In addition, the bus converter adds a large 32 MB of L4 cache to the sizable caches already offered on the Intel Itanium processors. This keeps the data close to the chip and offers improved performance.


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