Memory and backplane latencies
HP Integrity Superdome servers have been designed to reduce memory and backplane latencies, providing increased performance. There are three types of memory latencies within the HP Integrity Superdome system:
Memory latency within the cell refers to an application running on an nPartition consisting of a single cell board.
Memory latency between cells on the same crossbar refers to an nPartition consisting of up to four cells that reside on the same crossbar. For example, if there are four cells in the nPartition, ¼ of the requests go to the memory of the cell board in which the processor resides, and ¾ of the requests go to the memory of the other three cell boards.
• Memory latency between cells on different crossbars refers to an nPartition consisting of cell boards that do not all reside on the same crossbar. For example, if there are 16 cells in the nPartition, 1∕16 o f t h e r e q u e s t s a r e t o t h e m e m o r y o f t h e c e l l b o a r d i n w h i c h t h e p r o c e s s o r r e s i d e s . 3 ∕ 1 6 o f t h requests go to the memory of the other three cell boards on this same crossbar. Finally, the remaining 12∕16 of the requests transit across two crossbars. e
HP Integrity Superdome memory latency depends on the number of CPUs in the server and the location of their corresponding cell board. Assuming that traffic is equally distributed to all memory controllers and that cell boards are installed to minimize latency, the average memory idle latency (when nothing is executing on the system) and memory latency (load-to-use) are shown below.
Number of cell boards
Number of CPUs
Average idle load-to-use memory latency
4 (8 with mx2 Dual-Processor Modules)
8 (16 with mx2 Dual-Processor Modules)
16 (32 with mx2 Dual-Processor Modules)
32 (64 with mx2 Dual-Processor Modules)
64 (128 with mx2 Dual-Processor Modules)
The I/O subsystem
Each HP Integrity Superdome cell has an optional link to an I/O chassis. This enhances modularity and means there are no trade-offs for scaling of processors, memory, and I/O. Each cell connects to its remote I/O chassis through an I/O cable link.
The HP Integrity Superdome I/O subsystem has plenty of capability for today and expansion for tomorrow. Each I/O module consists of 12 PCI-X connections, divided among eight standard PCI-X and four high-bandwidth PCI-X slots, with an I/O controller ASIC and power. Each PCI-X slot has its own PCI-X bus—the standard PCI-X slot has 533 MB/s bandwidth, and the high-bandwidth PCI-X slot achieves a bandwidth of 1066 MB/s. The point-to-point connectivity allows the earliest detection, containment, and recovery from errors.
Any I/O module can support a core I/O card (required for each independent nPartition).