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Modeling Combinational Logic: Vector and Ranges

// Bit or range select of a port // or a signal is not allowed

sc_in<sc_uint<4> > data; sc_signal<sc_bv<6> > counter; sc_uint<4> temp; sc_uint<6> cnt_temp; bool mode, preset;

mode = data[2]; // not allowed //instead temp = data.read(); mode = temp[2];

counter[4] = preset; // not allowed cnt_temp = counter; cnt_temp[4] = preset; counter = cnt_temp;

  • A. Milenkovic

...

  • A. Milenkovic

Multiple Processes and Delta Delay

// File: mult_proc.h #include “systemc.h”

// File: mult_proc.cpp #include “mult_proc.h”

SC_MODULE(mult_proc) sc_in<bool> in; sc_out<bool> out;

{

void mult_proc::mult_proc1(){ c1 = !in; }

sc_signal<bool> c1, c2; void mult_proc1();

void mult_proc2(); void mult_proc3();

void mult_proc::mult_proc2(){ c2 = !c1; }

void mult_proc::mult_proc3(){

SC_CTOR(mult_proc) { SC_METHOD(mult_proc1); sensitive << in; SC_METHOD(mult_proc2); sensitive << c1; SC_METHOD(mult_proc3); sensitive << c2;

out = !c2; }

}

};

  • A. Milenkovic

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