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Write conceptual C/C++ model

Hand-over

Understand specification

Verify against specification

Partition design

Write testbench

Refine SystemC model to RTL

SystemC Design Methodology

System Designer

RTL Designer

Reverify

Reuse testbench

Synthesize

To implementation

  • A. Milenkovic

10

System Level Design Process

System Level model

Explore algorithms Verify against specifications

Refine

Timed model

Explore architectures Do performance analysis

Partition hardware / software

Software

Hardware

RTOS

Behavioral model Refine

Target code

RTL model

  • -

    Not synthesizable

  • -

    Event driven

  • -

    Abstract data types

  • -

    Abstract communication

  • -

    Untimed

  • -

    Event driven

    • -

      Synthesizable

    • -

      Algorithmic description

    • -

      I/O cycle accurate

    • -

      Clocked

    • -

      Synthesizable

    • -

      FSM

    • -

      Clocked

  • A. Milenkovic

11

Signals resolved, unresolved

VCD: Value Change Dump (IEEE Std. 1364)

updates after a delta delay Rich set of data types 2-value, 4-value logic

WIF: Waveform Interch. F.

ISDB: Integrated Signal Data Base

Modules SC_MODULE class

Event-base simulation Multiple abstraction levels

Processes SC_METHOD, SC_THREAD Ports: input, output, inout

Communication protocols Debugging support Waveform tracing

    • fixed, arbitrary size

  • Clocks

    • built-in notion of clocks

  • RTL synthesis flow

  • System and RTL modeling

  • Software and Hardware

SystemC Capabilities

  • A. Milenkovic

12

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