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Modeling Combinational Logic

// File: bist_cell.cpp #include “bist_cell.h”

}

void bist_cell::prc_bist_cell(){

Use SC_METHOD process with an event sensitivity list

// File: bist_cell.h #include “systemc.h” SC_MODULE(bist_cell) { sc_in<bool> b0,b1,d0,d1; sc_out<bool> z; void prc_bist_cell(); SC_CTOR(bist_cell) { SC_METHOD(prc_bist_cell); sensitive <<b0<<b1<<d0<<d1;

// File: bist_cell.cpp #include “bist_cell.h”

void b i s t _ c e l l : : p r c _ b i s t _ c e l l ( ) bool s1, s2, s3; {

s1 = !(b0&d1);

s2 = !(d0&b1); s3 = !(s2|s1);

s2 = s2&s1; z = !(s2|s3);

19

}

}

  • A. Milenkovic

}

z = !(!(d0&b1)&!(b0&d1))|! (!(d0&b1)|!(b0&d1)));

Modeling Combinational Logic: Local Variables

// File: bist_cell.cpp #include “bist_cell.h”

void bist_cell::prc_bist_cell(){

z = !(!(d0&b1)&!(b0&d1))|! !(d0&b1)&!(b0&d1)));

}

  • Local variables in the process (s1, s2, s3) do not synthesize to wires

  • Hold temporary values (improve readability)

  • Are assigned values instantaneously (no delta delay) – one variable can represent many wires (s2)

    • signals and ports are updated after a delta delay

  • Simulation is likely faster with local variables

// File: bist_cell.cpp #include “bist_cell.h”

void b i s t _ c e l l : : p r c _ b i s t _ c e l l ( ) bool s1, s2, s3; {

s1 = !(b0&d1);

s2 = !(d0&b1); s3 = !(s2|s1);

s2 = s2&s1; z = !(s2|s3);

}

  • A. Milenkovic

20

}

// File: xor_gates.cpp #include “xor_gates.h”

// File: xor_gates.cpp #include “xor_gates.h”

void bist_cell::prc xor gates(){ tap = bre ^ sty; }

_

_

void bist_cell::prc xor_gates(){ tap = bre.read() ^ sty.read(); }

_

Modeling Combinational Logic: Reading and Writing Ports and Signals

  • A. Milenkovic

21

// File: xor_gates.h #include “systemc.h” SC_MODULE(xor_gates) sc_in<sc_uint<4> > bre, sty; sc_out <sc_uint<4> > tap; void prc_xor_gates(); SC_CTOR(xor_gates) { SC_METHOD(prc_xor_gates); sensitive << bre << sty; {

}

  • Use read() and write() methods for reading and writing values from and to a port or signal

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