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UARTs in Xilinx CPLDs


The signals used by the receiver are given in Table 1. The receiver interfaces to the data bus dout[7:0] with the rdn signal. The controller can generate a rdn strobe if data_ready is true. The receiver is double buffered, allowing data to be held in the buffer register rbr[7:0] while data is shifted in serially into the receiver shift register rsr[7:0]. This provides the controller flexibility with bus read operations.

T h e r e c e i v e r d e t e c t s t h e c h a r a c t e r f r a m e a n d s t r i p s t h e s t a r t a n d s t o p b i t s . T h e n o _ b i t s _ r c v variable controls the word size. d

The clkdiv[3:0] register is used to control the time at which the data is decoded. The receiver uses the 16x local clock and decodes the value of start, data, and stop nits in the center of the data cells. To do this, the start bit initializes a count operation using clkdiv[3:0]. After detecting the low going edge on the start bit, the receiver counts the 16x clock to 8 and decodes, or samples the value of the signal. The clkdiv[3:0] register is then reset to 0, and subsequently counts the 16x clock to 16. This provides center sampling for the data and stop bits.

Three error detection signals are commonly used in UARTs. Parity Error indicates whether an even or odd number of "1s" are present in a data work. Overrun Error indicates whether the receive buffer register is overwritten by the receive shift register prior to the controller reading the receiver buffer register. Overrun Error is not implemented in the VHDL/Verilog source. Framing Error indicates if the stop bit is not High.

rst clk16x rdn dout[7:0] framing_error parity_error rbr[7:0]

Input Input Input Output Output Output Internal

Resets. 16x input clock. Read strobe. Output data bus. Framing error status signal. Parity error status signal.

Receiver buffer register - accepts data from data[7:0] and transfers it to rsr[7:0].



Receiver shift register - accepts data from rbr[7:0] and transfers it to sdo.

no_bits_rcvd clk1x_enable clk1x

Internal Internal Internal

Tracks character size and sequences receiver operation. Enable signal for registers clocked by clk1x. 1x clock used for internal operations.

Table 1: Receiver Signals




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XAPP341 (v1.3) October 1, 2002

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