UARTs in Xilinx CPLDs
The signals used by the transmitter are given in the table below. The transmitter interfaces to the data bus with the transmitter buffer register empty (tbre) and the wrn signals. The controller can generate a wrn strobe if tbre is high. The transmitter is double buffered, allowing data on din'7:0] to be written to the buffer register tbr[7:0] while data is being shifted out of the shift register tsr[7:0]. The transmitter generates a frame which consists of the idle state (high on sdo), low start bit, eight data bits, and a stop bit.
The no_bits_sent controls the word size and sequences the transmitter operations. To change the word size, change the value of no_bits_sent in the verilog source.
Table 2: Transmitter Signals
rst clk16x wrn sdo tbre
Input Input Input Output Output
Function Resets wrn1,wrn2,no_bits_sent, clkdiv[3:0],tbr[7:0],tsr[7:0] Local reference clock 16X the data rate Control signal which strobes data from din[7:0] to tbr[7:0] Serial data output
Status signal indication that the transmitter buffer register is empty
no_bits_sent clk1x_enable tbr[7:0] tsr[7:0] clkdiv[3:0]
Internal Internal Internal Internal Internal
Controls word_size and sequences transmitter operation Enables internal clock clk1x. Accepts data from din[7:0] and transfers data to tsr[7:0] Receives data from tbr[7:0] and shifts to sdo Used in generation of internal clock
VHDL (or Verilog) Code Download
VHDL (or Verilog) source code and test benches are available for this design. THE DESIGN IS PROVIDED TO YOU "AS IS". XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been verified on hardware (as opposed to simulations), and it should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise.
XAPP341 - http://www.xilinx.com/products/xaw/coolvhdlq.htm
Initial Xilinx release.
Added VHDL Code Download link.
Changed XCR3128 to XCR3128XL in Summary.
Updated device targets
The following table shows the revision history for this document.
XAPP341 (v1.3) October 1, 2002