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CPSC 410/611: Operating Systems

Projects: Exceptions + Interrupts

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Interrupt Descriptor Table

! Interrupt Vector Table x86-style:

! processor exceptions, hardware interrupts, software interrupts

IDT

! 256 entries: Each entry contains address (segment id and offset) of interrupt handler (interrupt service routine).

exception handler

! The first 32 entries reserved for processor exceptions (division by zero, page fault, etc.)

! Hardware interrupts can be mapped to any of the other entries using the Programmable Interrupt Controller (e.g. 8259 PIC, see later)

interrupt handler

Description Division By Zero Exception Debug Exception Non Maskable Interrupt Exception Breakpoint Exception Into Detected Overflow Exception

Error Code? No No No No No

Out of Bounds Exception Invalid Opcode Exception No Coprocessor Exception Double Fault Exception

No No No Yes

Coproc. Segment Overrun Exception

No

Bad TSS Exception Segment Not Present Exception Stack Fault Exception General Protection Fault Exception Page Fault Exception Unknown Interrupt Exception Coprocessor Fault Exception Alignment Check Exception (486+)

Yes Yes Yes Yes Yes No No No

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No

Processor Exceptions

Exception # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 to 31

Machine Check Exception (Pentium/586+)

Reserved Exceptions

No

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