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Compound Logic Expressions:

Evaluated left-to-right except as modified by parenthases.

Composed of the following –

Signal names – evaluates to the state of the signal in current vector

Register Names – evaluates to current state of register

Parenthases

State characters (from OVF states)

Logical Operators:   AND (&), OR ( | ), NOT (~)

Equivalence Operator:  =

Some Examples:

(pin1=1)&((pin2=0)|(pin3=Z))

True if pin1 is a 1 and either pin2 is a 0 or pin3 is a Z.

(pin1 & (~pin2 | (pin3=Z))

Equivalent to above

In addition to being able to reference a signal’s current state in these expressions, the state from a vector prior-to or after the current vector can also be referenced. The syntax for this is: Signal(+/-n).

(pin1 & (pin2(-3) | pin3) = 1)

True if pin1 is 1 and either pin2 was 1 3 vectors ago or

    pin3 is 1

(SIGA(-8) & SIGA(+8) & (SIGB=Z))

True if SIGA was 1 8 vectors ago and will be 1 8 vectors

from now and SIGB is a Z

Examples of Use:

BIDIRECT_CONTROL bidi[7:0] = input WHEN (SIG1=0)&(SIG7=0) ;

BIDIRECT_CONTROL pin1, pin2, pin3 = output WHEN

(enb(-1)=1) & (enb=1);

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