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FORMATTING OUTPUT VECTORS

TESTBENCH OUTPUT - VERILOG:

Two optional variations are available with Verilog testbench outputs.  The first is a simple, linear, in-line testbench in which all of the stimulus and expected output state checking is performed in one large module.  This format is invoked with the following statement, along with its optional parameters:

 SIMULATOR verilog_tb,

   -VERBOSE,

   -INHIBIT_CHECKING,

   TESTBENCH_MODULE = "Top_Module",

   COMPONENT_MODULE = "CompUSA",

   INSTANCE_NAME = "U4",

   TIMESCALE = "1ns/100ps",

   OUTPUT_GROUP = "pin3, pin4, .. "

   PSEUDO_SIGNAL = "pinname",

   TERMINATE_RUN = "$finish",

   MAX_MISMATCHES = "nn"

   ;

The second Verilog testbench option separates the main Verilog testbench control loop from the stimulus/expected state data using the readmem feature in Verilog to read the data from external files. This format is invoked as follows:

 SIMULATOR verilog_tb_readmem,

  . . .

   INPUT_GROUP = "pin1, pin2, .. "

   DATAFILES = "datafilename",

   ;

The optional parameters shown are those in addition to those for the Verilog_tb format listed above.  

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