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FORMATTING OUTPUT VECTORS

TESTBENCH OUTPUT - VHDL:

Two optional variations are available with VHDL testbench output also.  The first is a simple, linear, in-line testbench in which all of the stimulus and expected output state checking is performed in one large module.  The second uses textio to read the stimulus and expected output states from an external file.  These formats are invoked with the following statement, along with the optional parameters:

 SIMULATOR vhdl_tb, {  or SIMULATOR vhdl_tb_tio, }

   -93,             { for vhdl_tb_tio only }

   LIBRARY = "NULL",

   USE = "NULL",

   UNITS = "ns",

   CONFIG_FILE = "NULL",

   CONFIG_NAME = "",

   ARCHITECTURE = "testbench",

   INSTANCE_NAME = "U0",

   ENTITY = "_tb",

   COMPONENT = "design",

   COMPONENT_ARCHITECTURE = "STRUCTURAL_VIEW",

   NINE_VALUE = "OFF",

   DONT_CARE = 'X',

   BIT_TYPE = "STD_LOGIC",

   BIT_VECTOR = "STD_LOGIC_VECTOR",

   RESULT_TYPE = "STD_LOGIC",

   RESULT_VECTOR = "STD_LOGIC_VECTOR",

   STATE_CHARACTERS = "10HLUXZW-",

   SEVERITY = "WARNING",

   LIST_ERRORS = "BY_PIN",     { vhdl_tb only }

   PSEUDO_SIGNAL = "pin1, pin2",

   MAXLINES = "nnnnnn",     { vhdl_tb only }

   INPUT_GROUP = "pin3, pin4",

   MAX_MISMATCHES = "nn",

   OUTPUT_GROUP = "pin5, pin6",

   EQUIV_SIM_STATES = "a->b, c->d, e->f, ...",

   BUFFER_PORTS = "pin7",

   LINKAGE_PORTS = "pin8, pin9" ;

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