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FORMATTING OUTPUT VECTORS

TESTER FORMATS SUPPORTED:

INVOCATION:

A number of canned output formatters for physical device testers are available with vtran (a vtran-t license is required for these).  A tester output format is specified in the TVF_BLOCK with:

TESTER_FORMAT format [params];

Some canned output tester formats currently available are summarized below:

Teradyne Catalyst, J750, J971/973, FLEX

LTX

ITS9000

Credence - SWAV

Agilent (HP) 83000/93000

Agilent (HP) 3070 - PCF

IMS

Advantest T66xx, T33xx

The most common source formats of simulation or ATPG-generated vectors for translation to these tester formats are:

Verilog VCD or EVCD files - print-on-change vector data

WGL or STIL files - cycle-based vectors

Translating VCD (EVCD) files requires significantly more information in the vtran command file than do WGL or STIL file translations.  For VCD (EVCD) translations this information normally includes:

Signal Direction (INPUTS, OUTPUTS, BIDIRECTS)

Cycle time (CYCLE)

Collapsing mechanism (ALIGN_TO_xx or TEMPLATE_CYCLIZATION )

Bidirectional data separation (BIDIRECT_CONTROL)

State character mapping (STATE_TRANS)

Timing for signals (PINTYPE statements)

Tester format & optional parameters (TESTER_FORMAT …)

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