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EXAMPLES / ISSUES

EXAMPLE1:

This example shows vtran reading a Verilog VCD file, which is print-on-change.  The vectors are translated to Verilog testbench format.   Signals are top-level pins.

ovf_block begin  orig_file "example1.vcd";

 script_format verilog_vcd;

 inputs         clock, reset, driving_data;

 outputs        address[18:0], we, oe, data_echo[21:0];

 bidirects      data[21:0];

 END

PROC_BLOCK

 BEGIN

 bidirect_control data = output when driving_data = 1;

 cycle = 20;

 check_window * @ 17, 19;{ look at outputs here }

 END

TVF_BLOCK

 BEGIN

 delete_pins  driving_data;

 simulator  Verilog_tb,

-verbose,

testbench_module = "bluehole",

timescale = "1 ps",

max_mismatches = "10",

terminate_run = "$finish";

 target_file    "example1.tb";

 END

EXAMPLE 2:

In this example, the OVF is an EVCD (Extended VCD) file.  These files are similar in format to VCD files, except that they provide data directional information for bidirects by using different state characters and strength values.  Note the state translations required due to this, and the fact that bidirect_control is

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