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EXAMPLES / ISSUES

EXAMPLE 2 (cont.):

OVF_BLOCK   

 BEGIN

 ORIG_FILE  "ncsim.evcd" ;

 SCRIPT_FORMAT verilog_vcd;

 INPUTS CFG[55:0], SELF, COMPLETE, READY, C_T, GNT, IDSEL,

   KEEPOUT, M_CBE[3:0], M_READY, M_WRDN, PCLK, REQUEST, REQ,

   RST_I, SUB_DATA[31:0], S_ABORT, S_READY, S_TERM;

 OUTPUTS ADDR[31:0], ADDR_VLD, BACKOFF, BASE_HIT[7:0], B_B

   STOPQ_N, S_CBE[3:0], S_DATA, S_DATA_VLD, S_SRC_EN, S_WR

   TRDYQ_N INTA_O, REQ_O;

 BIDIRECTS ADIO[31:0], AD_IO[31:0], CBE_IO[3:0], CLK,

   IRDY_IO, PAR_IO, PERR_IO, RST, SERR_IO, STOP_IO, TRDY_IO;

 END;

PROC_BLOCK

 BEGIN

 CYCLE 15;    

 CHECK_WINDOW * @ 12;   

 STATE_TRANS pure_inputs

  'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1',

  'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X',

  '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X',

  'c'->'X', 'f'->'Z', 'F'->'Z';

 STATE_TRANS pure_outputs

  'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X',

  'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X',

  '?'->'X', 'A'->'1', 'a'->'X', 'B'->'0', 'b'->'X', 'C'->'0',

  'c'->'1', 'f'->'Z', 'F'->'Z';

   STATE_TRANS bidir_inputs

  'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1',

  '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X',

  'c'->'X';

 STATE_TRANS bidir_outputs

  'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'X',

  '?'->'X', 'A'->'1', 'a'->'X', 'B'->'0', 'b'->'X', 'C'->'0',

  'c'->'1', 'f'->'Z', 'F'->'Z';

 END;

TVF_BLOCK BEGIN

 TARGET_FILE = "p_evcd_tb.v" ;

 SIMULATOR verilog_tb, -VERBOSE

   TESTBENCH_MODULE = "_tb",

   COMPONENT_MODULE = "pcim_c",   { unpackage }

   INSTANCE_NAME = "DUT",

   TIMESCALE = "1 ns/1 ps",

         MAX_UNMATCHED = "500",

   TERMINATE_RUN = "$finish";

END;

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