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EXAMPLES / ISSUES

EXAMPLE 3:

This vtran command file example illustrates the simplicity of translating a WGL file to a VHDL testbench.  The WGL file contains all of the signal names, directions, timing information and separation of bi-directional data so this information need not be specified in the command file.

ovf_block

begin

orig_file = "s0.wgl";

tabular_format wgl;

end;

proc_block

   begin

   state_trans bidir_outputs '-'->'X';

   state_trans bidir_inputs '-'->'Z';

   end;

tvf_block

begin

target_file = "tvf0";

simulator vhdl_tb

MODULE = "XXXX",

max_mismatches = "12"

EQUIV_SIM_STATES = "H->1, L->0";

end;

end;

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