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EXAMPLES / ISSUES

EXAMPLE 4:

Vtran reads a VCD print-on-change file, does some timing modifications, separates bidirectional data and produces a NANOSIM file set.

ovf_block

   begin

   orig_file "example3.vcd";        { vcd vector file name }

   script_format verilog_vcd_f;  { full path on signals }

   inputs top.oak.clockin,

     top.oak.lrstp, top.oak.lint0p, top.oak.lint1p,

     top.oak.lint2p, top.oak.omemsz4p, top.oak.biuser0p,

     top.oak.biuser1p, top.oak.lnmip, top.oak.bbootp,

     top.oak.btrapreqp, top.oak.bfloatpp, top.oak.bfloatdp,

     top.oak.bwaitp,top.oak.bextpp,top.oak.bloc1.dout[15-0],

     top.oak.bloc0.dout[15-0], top.oak.bloc1_1.dout[15-0],

     top.oak.bloc0_1.dout[15-0];

   outputs top.oak.denwrp1;  { control of gexdbp bus }

   outputs top.oak.__225;    { control of gip bus }

   bidirects top.oak.gexdbp[15-0], top.oak.gip[15-0];

   outputs top.oak.pprp, top.oak.piackn, top.oak.pmemenp,

     top.oak.pdummyp,top.oak.pstatusp[3-0], top.oak.pbkendp,

     top.oak.cusero1p, top.oak.pextip;

   end;

proc_block

   begin

   bidirect_control  top.oak.gexdbp[15-0] = input when

     top.oak.denwrp1 =1, default_input=Z, default_output='U';

   bidirect_control  top.oak.gip[15-0] = input when

     top.oak.__225 =0, default_input=Z, default_output='U';

   cycle 40;

   edge_align top.oak.clockin @ 10, 27;  { force edges here }

   edge_shift top.oak.lnmip @ -4.5, 5;   { shift edges }

   check_window * @ 38 39;{ check outputs at 38 ns }

   end;

tvf_block

   begin

   header 500;  resolution 0.01;

   simulator nanosim;

   target_file "tvf3.vec"; command_file "tvf3.cmd";

   alias "top.oak."="" ;  { remove path prefix from signals }

   end;

end;

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