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EXAMPLES / ISSUES

EXAMPLE 5:

Read a VCD file and translate to an HP93000 test program with timing.

OVF_BLOCK

 BEGIN

 ORIG_FILE      "s4.vcd";{ name of input vcd file }

 SCRIPT_FORMAT verilog_vcd;{ the format of the input file }

 INPUTS  C2_LBUSRDY  , C1_RSFTEN  , C2_CPUACKN  ;

 OUTPUTS  S2_EVTSET2  , S2_EVTSET1  , S2_EVTSET0  ,

   S1_CEXEC0  , S2_CDI15  , S2_CDI14  , S2_CDI13  ,

   S2_CDI8  , S2_CDI7  , S2_CDI6  , S2_CDI5  ;

 BIDIRECTS  L2_LDB31[2:0]  , L2_LDB30  , L2_LDB29  , L2_LDB28  ,

   L2_LDB27  , L2_LDB26  , L2_LDB25  , L2_LDB24  , L2_LDB23  ,

   L2_LDB22  , L2_LDB21  , L2_LDB20  , L2_LDB19  , L2_LDB18  ,

   L2_LDB17  , L2_LDB16 ;

 INPUTS  T2_TLBMIS  , T2_TLBERR  , YCMCPU  , YA_ASM  ,

   YA_TM2  , E2_INTREQ2  , E2_INTREQ1  , E2_INTREQ0  ,

   U2_ASRTBMK  , U2_BRKTYP0  , U2_BRKTYP1  , Y1_STPCPU;

 OUTPUTS  S2_LAB31  , S2_LAB30  , S2_LAB29  , S2_LAB28 , S2_LAB27,

   S2_LAB26  , S2_LAB25  , S2_LAB24  , S2_LAB23  , S2_LAB22  ,

   S2_YAB2  , S2_YAB1  ;

 OUTPUTS  EMWHHP  , EMWBHP  , EMWLHP  , EMWBLP  ;

 END;

PROC_BLOCK

 BEGIN

 STATE_TRANS 'x'->'X', 'z'->'Z' ;

 state_trans outputs '0'->'L', '1'->'H', 'Z'->'M', 'z'->'M';

 BIDIRECT_CONTROL L2_LDB31 , L2_LDB30 , L2_LDB29 ,

   L2_LDB28 , L2_LDB27 , L2_LDB26 , L2_LDB25 , L2_LDB24 ,

   L2_LDB23 , L2_LDB22 , L2_LDB21 , L2_LDB20 , L2_LDB19 ,

   L2_LDB18 , L2_LDB17 , L2_LDB16 = output when EMWHHP = 1;

 CYCLE = 100;

 ALIGN_TO_CYCLE 100 ALL_INPUTS @ 20, ALL_OUTPUTS @ 95, YCMCPU @ 40 ;

 PINTYPE NRZ * @ 5;     { drive all inputs at 5 }

 PINTYPE STB * @ 95, 96;    { strobe all outputs at 95 }

 PINTYPE RZ YCMCPU @ 0, 50;  { clock pin behavior }

 END;

TVF_BLOCK

 BEGIN

 TESTER_FORMAT hp93000, -auto_group,

   REPEAT_THRESHOLD = "32",

   MAX_LINE_LENGTH = "120",

   Use_Timeset = "DefTim",

   DVC_FILE = "s4.dvc";

 TARGET_FILE    "s4.avc";

 END;

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