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EXAMPLES / ISSUES

EXAMPLE 7:

Vtran reads a VCD file and translates some of the pins to a WGL file.  Processing collapse to cycle data, separate bidirect data, then define timing for pins.

ovf_block

 begin

 orig_file "example6.vcd";

 script_format verilog_vcd;

 inputs slpor, spltstme, smodclk, sxsxtalb,

    sxssiz[1:0], sxdbin[15:0], ihaltb;

 inputs swidbus, sb41b, s61, sb3ab, int_211; ( 3-S contrls }

 outputs squot, islhae, islxbav, sbxbavb,

    sbwc1, senrefb, sptedat[7:0], {8 bits, hex}

    sreset, sfsrsto, scpstdat; {TMP as output. It IS a bidi}

 bidirects iaddr[23:0], idata[15:0];

proc_block

 begin

 align_to_step 12.500, 12.400;  { convert to cycle data }

 cycle = 12.500;

 bidirect_control iaddr[23:19] = output when (s61 | (~sb3ab))=1,

      default_input = Z, default_output = X;

 bidirect_control iaddr[18:0] =  output when ~sb3ab = 1,

      default_input = Z, default_output = X;

 bidirect_control idata[15:12] = output

      when ((swidbus | sreset) | (~sb41b)) = 1,

      default_input = Z, default_output = X;

 bidirect_control idata[11:0]=output when (swidbus|(~sb41b))=1,

      default_input = Z, default_output = X;

 state_trans 'x'->'X';

 separate_timing;

 pintype nrz slpor, spltstme, smodclk, sxsxtalb,

    sxssiz[1:0], sxdbin[15:0], ihaltb @ 5.0;

 pintype nrz iaddr[23:0], idata[15:0] @ 5.0;

 pintype stb * @ 12.4;

 end;

tvf_block

 begin

 delete_pins swidbus, sb41b, s61, sb3ab, int_211; ( contrls }

 simulator wgl;

 busformat = hex;

 resolution 0.1;

 target_file "tvf6.wgl";

 end;

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