READING VECTOR FILES
One vector line per cycle (period). Timing of individual pin transitions may be contained in a data block separate from the vector data. Examples would be most all testers, WGL, STIL, TSTL2, etc.
EVENT-DRIVEN (PRINT-ON-CHANGE) Vectors:
For every time in which there is a state transition event, a new vector statement is present. All timing information is contained in the time stamps of the vector data. Examples would be Verilog VCD/EVCD files, EPIC .vec files, etc.
FLAT VECTOR FILES:
Contains no higher-level language constructs such as loops, macros or subroutines. Also no algorithmic pattern representations. Examples are EPIC .vec files, Verilog VCD files, Mentor log files, etc.
HIERARCHICAL VECTOR FILES:
Vector data files use high-level language constructs like loops, macros, algorithmic pattern representations, etc. Examples are most tester formats, WGL, TSTL2, STIL, etc. Note that the Hierarchical vector files are also typically cycle-based files.