Xilinx Implementation Tutorial
Michael Bales School of Electrical and Computer Engineering Georgia Institute of Technology
The purpose of this tutorial is to provide exposure to commonly implemented components in the Xilinx ISE environment. Components we’ll look at include global clock buffers, tri-state buffers, and block RAM (BRAM). A few notes on using timing constraints are also provided.
Clock buffers are used to increase the fanout capacity of a clock signal, and to minimize skew. They also help the synthesis tools identify which signals are global clocks in complex designs. They are most easily instantiated directly as components.
From Xilinx’s Libraries Guide “lib.pdf”
Component Declaration for BUFG should be placed
after architecture statement but before begin keyword
port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component;
Component Instantiation for BUFG should be placed
in architecture after the begin keyword BUFG_INSTANCE_NAME : BUFG port map (O => user_O,
I => user_I);
Frequently in a design (particularly in designs that manipulate large amounts of data), several computing modules may need access to the same data at different times. For instance, you may have an image processor. Each pixel of the image is stored in RAM. The processor has to fetch each pixel, perform some operation on it, and store the new value in the same RAM location. Then, perhaps you want the data compressed, so a compressor grabs the post-processed data from RAM, encodes it, and outputs the final stream serially. The image processor and the compressor need to access the same RAM, but not at exactly the same time. Each needs independent control of the address and control lines.
Tri-state buffers allow modules to control the same signals at different times without interfering with each other. If each module were connected to the signals directly, those signals would have two (or more) drivers, and that would cause problems.
Here is the VHDL code for a generic tri-state buffer:
entity gen_tribuf is generic(width : positive); Port ( pass : in STD_LOGIC; i : in STD_LOGIC_VECTOR (width-1 downto 0);
: out STD_LOGIC_VECTOR (width-1 downto 0));
e n d g e n _ t r i b u f ;
architecture Behavioral of gen_tribuf is constant hi_imp : STD_LOGIC_VECTOR(width-1 downto 0) := (others => 'Z'); begin o < = i w h e n p a s s = ' 0 ' e l s e h i _ i m p end Behavioral; ;