By instantiating these between each module and the shared signals, a state machine or other control logic can manage the ‘pass’ signal so that only the correct module controls the shared signals at any time.
Block RAM (BRAM)
Many modern FPGAs have two types of memory elements available. Distributed RAM takes the form of flip-flops that are created within the general-purpose logic fabric of the chip. This is good for storing small amounts of data, making registers, shift registers, etc. Block RAM is dedicated, configurable memory with address, data, and control ports. If your design stores and manipulates a lot of data, Block RAM (BRAM) is the way to go. Otherwise, the synthesizer may try to generate enough storage out of the FPGA’s logic slices, which could cause you to run out of room for the logic portion of your design.
The BRAM in Xilinx’s FPGAs is fairly versatile. For the Virtex-4, each block consists of 18 kbits, and can be configured in any aspect ratio from 16k single bits, 8k 2- bit words, up to 512 36-bit words. Also, blocks can be automatically chained together to form larger memories. For example, by specifying a RAM with 1024 words that are 36 bits each, the synthesis tools would connect two blocks together.
BRAM also supports dual-ports. Each port has its own data in, data out, address bus, and clock, as well as EN and WE control lines. The two ports can even vary in data word width.
To get the synthesizer to recognize that BRAM should be used instead of distributed RAM, you must use a particular entity declaration and architecture. A simple example is shown here:
entity my_ram is port (
clka : in std_logic; ena : in std_logic; wea : in std_logic; addra : in std_logic_vector(7 downto 0); dia : in std_logic; doa : out std_logic);
architecture Behavioral of my_ram is type ram_type1 is array (255 downto 0) of std_logic; signal RAM1 : ram_type1; begin process (clka) begin if (clka'event and clka = '1') then if (ena = '1') then if (wea = '1') then RAM1(conv_integer(addra)) <= dia; end if; d o a < = R A M 1 ( c o n v _ i n t e g e r ( a d d r a ) ) ;
end if; end process;