X hits on this document

9 views

0 shares

0 downloads

0 comments

3 / 5

The BRAM described above uses a single port, and consists of 256 single-bit entries. The number of addresses is controlled simply by the address bus width, and by the array size of ram_type1. Likewise, the word width is controlled by the data bus widths, and again in the element size of the type ram_type1. Also note that this BRAM writes first, then places data on the output bus. Read-then-write and no-change synchronizations are also supported. Here is an example of a dual-port BRAM.

Document info
Document views9
Page views9
Page last viewedSat Oct 29 00:01:44 UTC 2016
Pages5
Paragraphs58
Words1555

Comments