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entity vector_ram is port(clka : in std_logic; clkb : in std_logic; ena : in std_logic; enb : in std_logic; wea : in std_logic; web : in std_logic; addra : in std_logic_vector(8 downto 0); addrb : in std_logic_vector(8 downto 0); dia : in std_logic_vector(35 downto 0); dib : in std_logic_vector(35 downto 0); doa : out std_logic_vector(35 downto 0); dob : out std_logic_vector(35 downto 0)); end vector_ram;

architecture syn of vector_ram is

type ram_type3 is array (0 to 511) of std_logic_vector(35 downto 0); shared variable RAM3 : ram_type3; begin

process (CLKA) begin if CLKA'event and CLKA = '1' then if ENA = '1' then if WEA = '1' then RAM3(conv_integer(ADDRA)) := DIA; end if; DOA <= RAM3(conv_integer(ADDRA));

end if;

end if; end process;

process (CLKB) begin if CLKB'event and CLKB = '1' then if ENB = '1' then if WEB = '1' then RAM3(conv_integer(ADDRB)) := DIB; end if; DOB <= RAM3(conv_integer(ADDRB));

end if;

end if; end process;

end syn;

Other BRAM configurations, as well as code samples for many other useful synthesis constructs, can be found in ISE under Edit-> Language Template menu, in the VHDL->Synthesis Constructs -> Coding Examples folder. More information about Virtex-4 BRAM resources can be found in the Virtex-4 User’s Guide.

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