Timing Constraints and Synthesis Effort
We often want to maximize the operating frequency of a design, or at least reach a minimum target speed. While pipelining and parallel processing are two tools that help us with those tasks, maximum operating frequency is heavily dependent on how the place and route tools map a design onto the FPGA logic fabric. There are two primary means for telling the tools what areas to focus on: timing constraints and synthesis effort.
Synthesis effort is a global effect, and is good to use if you have extra logic space available on the FPGA and want to squeeze more speed out of the design. Alternatively, you can reduce the footprint of the design at the expense of speed. By right-clicking on the Synthesize menu in the Processes window and selecting Properties, you can specify what optimization you’re after. There are two properties to adjust: Optimization Goal and Optimization Effort. Optimization Goal lets you specify whether you’re more worried about speed or area. Optimization Effort tells the computer how much computing power you’re willing to throw at the problem. Setting this to ‘High’ tells the computer that you’re willing to wait a while (sometimes a long while) for even more speed or less area. Sometimes the effect is very small, and may not be worth the wait. However, changing the Optimization Goal can have a drastic impact on size versus speed.
Another synthesis option to consider is Resource Sharing (found by right-clicking on Synthesize, selecting Properties, and clicking on the HDL Options category, 2nd from bottom). If resource sharing is selected, the synthesizer will allow logic functions to share common logic paths (for example, two separate adders may be allowed to share some adder circuitry). Resources sharing usually results in slower performance, but saves area. If speed is what you’re after, turn off Resource Sharing.
Specifying a timing constraint tells Place & Route what you’re timing requirements are for particular signal or path. P&R will then spend extra effort looking for ways to place logic blocks and route signals to meet your goal. This tool should be used carefully; if your constraints are too stringent, or if you specify too many constraints, P&R may not find a solution. Be selective. However, placing one or two constraints on global clock signals or long, vital data paths very often improves speed considerably.
Timing constraints are most easily added using the Constraints Editor, under User Constraints in the Processes window. Here, you can enter the desired period for clock signals (under the Global tab), and desired setup and offset times for signals (under the Ports tab). Simply enter your values in the editor, save, and close. The next time you run Place & Route, your criteria will be taken into account.