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Chapter 2: Custom single-purpose processors - page 10 / 29

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Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Sequential logic design

A) Problem Description

You want to construct a clock divider.  Slow down your pre-existing clock so that you output a 1 for every four clock cycles

0

1

2

3

x=0

x=1

x=0

x=0

a=1

a=1

a=1

a=1

a=0

a=0

a=0

a=0

B) State Diagram

C) Implementation Model

Combinational logic

State register

a

x

I0

I0

I1

I1

Q1

Q0

D) State Table (Moore-type)

1

0

1

1

1

1

1

0

1

1

1

1

1

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

1

0

0

0

0

0

0

Inputs

Q1

Q0

a

Outputs

I1

I0

1

0

0

0

x

Given this implementation model

Sequential logic design quickly reduces to combinational logic design

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