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Chapter 2: Custom single-purpose processors - page 11 / 29

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Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Sequential logic design (cont.)

0

0

1

   Q1Q0

I1

 I1 = Q1’Q0a + Q1a’ + Q1Q0’

0

1

1

1

0

1

0

00

11

  10

a

01

0

0

0

1

0

1

1

 00

   01

  11

a

1

    10

I0

   Q1Q0

I0 = Q0a’ + Q0’a

0

1

0

0

0

1

1

0

0

00

01

11

   10

x = Q1Q0

 x

0

1

0

a

Q1Q0

E) Minimized Output Equations

F) Combinational Logic

a

Q1

Q0

  I0

  I1

x

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