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A Prototype Optical Tracking System Investigation and Development - page 140 / 170

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140 / 170

126

4

3

2

1

A

A

3V3

2

P0VREG102

OUT

VREG1 IN

3

C38

1uF

GND

1

P0VREG103

P0VREG101

5V0

P0C3801 P0C3802

C37

P0C3702 P0C3701

10V 100uF Tant

GND

GND

GND

Use ADP3338AKC-3.3 for 3.3V regulation

ADP3338

Board Voltage Regulation 5V to 3.3V

B

B

R19

3V3

3V3 1V2

3V3

FET1

P0R1902

P0R1901

BF RESET

_

C42 1nF

P0C4201 P0C4202

1K

6

P0RS3V306

5

P0RS3V305

1 4

RESET Ct

Vcc

Sense

P0RS3V301

P0RS3V304

MR

3

P0RS3V303

IC Supervisor 3.3V RS3V3

GND

2

P0RS3V302

RS1V2 IC Supervisor 1.2V

5

P0RS1V205

1 4

RESET Ct

Sense

P0RS1V201

P0RS1V204

GND

2

P0RS1V202

GND

6

P0RS1V206

Vcc

MR

3

P0RS1V203

P0SW102

SW1

P0SW101

GND

P0SW103

GND

C40

6.3V 100uF Tant

P0C4002 P0C4001

C41 10uF

GND

C43 6.3V 100uF Tant

P0C4101 P0C4102

1V2

P0C4302 P0C4301

1 2 3

P0FET101

P0FET102

P0FET103

S S S

P0L102

C44 10uF

P0C4401 P0C4402

D D D D

5 6 7 8

P0FET105

P0FET106

P0FET107

P0FET108

G MOSFET L1

4

P0FET104

P0L101

Inductor 10uH

P0D102

D1 1N5819

P0D101

Keep trace short VROUT

C

GND

GND

Place caps as close as possible to FET

C

Master Reset Logic

GND

Core Voltage Regulation

Black Spot Schematics

D

Revision A.3

Camera Module - Power, Clocks and Comms

Number Version 2.0 (with mods)

Title

Size A

P0R2002

R20 10M

P0R2001

Y1

XTAL

C46 18pF

12

10Mhz C45

18pF

P0Y102

P0Y101

P0C4601 P0C4602

P0C4501 P0C4502

Blackfin Clock

CLKIN

D

5 Cris Lovell-Smith

Sheet 3of Drawn By:

13/01/2009 M:\dev\..\Power and Clocks.SchDoc

Date: File:

4

3

2

1

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