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A Prototype Optical Tracking System Investigation and Development - page 70 / 170

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70 / 170

(bytes)

Blackfin BF531

400

32K

16K

Blackfin BF532

400

48K

32K

Blackfin BF533

600

80K

64K

Blackfin BF534

500

64K

64K

Blackfin BF536

400

64K

32K

Blackfin BF537

600

64K

64K

Blackfin BF561

600

32K / core

64K /core

Ethernet M C Ethernet M C

Dual core, 128K bytes L2 SR M

Table 5.1 A selection of the Blackfin family that Analog Devices lists as supported by GNU tools is shown here. The Blackfin BF533 has the greatest amount of internal L1 SRAM of this selection.

(MHz)

Program

SR M

SR M

(bytes)

56

Name

Max. Clock

Max.

Black Spot Hardware

Max. Data

Notes

of I/O pins and peripherals. For example, the Blackfin BF533 has up to 16 general purpose I/O lines and contains a U RT module, Real Time Clock, and other specialised peripher- als. Many Blackfin chips are well supported by the GNU GCC open source compiler. They are designed for video applications and have custom instructions for processing video data as well as a bus interface suited to connecting to CMOS image sensors. These processors have a strong support community on the internet. In addition to this an application note

from

nalog Devices describes connecting a CMOS sensor to the Blackfin [75] and one of

the author’s supervisors, Dr Michael Hayes, had prior experience using these chips.

There are many processors in the Blackfin range and a number are supported by the GNU GCC compiler at the time of part selection. Table 5.1 lists these chips and their maximum clock rates, and memory capacities. Since part selection, nalog Devices has introduced many more processors to this family and the GCC compiler is increasing support for them.

Of particular note is the Blackfin BF533 and the Blackfin BF561.

t the time of writing, the

Blackfin BF533 has the most internal high-speed “Level 1” (L1) SR

M of the family1 and

this is BF561

attractive as it could lead to a system that does not require SDR M. The Blackfin is the only chip in the family that has two processing cores in the same physical

package. Using this chip could allow a greater range of algorithms to be due to the extra processing facilities, however, designing algorithms to run

implemented in parallel on

separate processors is not trivial and would add considerable complexity to the software.

For the prototype, the Blackfin BF533 was chosen primarily due to the amount of R M that it has.

1The BF561 has more SR M but a portion of this is classed as “Level 2” SR M and runs at half the clock speed of L1 SR M and with longer latencies.

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