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A Prototype Optical Tracking System Investigation and Development - page 77 / 170

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5.3 Design considerations

63

10 MHz Clock

133 MHz

Data

Control

Clock

bus

Signals

SDRAM

Blackfin DSP

Shared bus with other camera modules.

To Hub

MT9V022 Image Sensor

Image Sensor Control Bus (TWI)

Control Signals

8/10 bit parallel Image Data

26.6 MHz Clock

Figure 5.4 A possible design consisting of an image sensor, Blackfin DSP, and external SDRAM.

Image Sensor Register Control Bus (TWI)

MT9V022 Image Sensor

Control Signals 8/10 bit parallel Image Data 26.6 MHz Clock

Blackfin DSP

Shared bus with other camera modules.

To Hub

10 MHz Clock

Figure 5.5 The approach chosen uses a CMOS sensor and Blackfin DSP with internal SRAM.

facilities of the Blackfin could mitigate this at the expense of designing the software to work with partial image frames. Due to the limited time available to produce a prototype, the author’s hardware design experience, and the need to produce a board with the greatest potential to work correctly, external SDR M was discarded.

5.3.6

System with internal SR M

system using the Blackfin BF533 DSP with internal SR M only (Figure 5.5) was chosen

for the reasons discussed above.

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