6.1 Physical layer
Figure 6.1 Camera modules communicate over a shared bus with the PC.
stances data was lost due to the PC not processing the module data fast enough.
robust design was favoured using a flow control line (CTS - Clear to Send). This line is as- serted by the FTDI chip when the PC cannot service the incoming data buffer fast enough. It is monitored by all the camera modules and when the line is asserted, the module that is
currently using the bus ceases to transmit until the line is released by the FTDI chip.
The system is designed so that the data path from the camera modules to the Soft Hub is shared. This is achieved by implementing a scheme similar to digital Time Division Multiplexing (TDM) . In this approach time slots are defined for each module within a cycle defined by the camera frame period. module may only transmit data when its time slot is active. Once a module has finished using the bus the next time slot begins and therefore the time slots do not have a fixed duration (the difference between this approach and TDM). Having variable length time slots is an advantage in that if a module has no
data to transmit then it can immediately cease using the bus, freeing it for the next module. However, a disadvantage to this approach is that theoretically a module may take control of the bus for an inappropriately long time, causing other modules to become overloaded with data they wish to send. The control algorithm in the firmware can be written to avoid this situation.
Initially, the Soft Hub signaled which time slot was active using a RequestDataPacket sent to each module in turn. Each module responded with the data and appended a spe- cial packet to indicate that it had finished its transmission. Therefore, each slot involved a communication from the Soft Hub and reply from a Black Spot module. lthough this approach works in principle, it proved to be impractical as it relies on a low latency be- tween the Soft Hub and camera modules. Using the FTDI drivers for Microsoft Windows