Time Slot Period
Figure 6.2 In a scheme that requires the Soft Hub to request data from a camera module the time taken to receive the data is the sum of the time it takes to transmit the packet, the latency in the packet transmission, the time it takes for the Black Spot module to send the packet reply, and the latency in the Black Spot reply.
it was difficult to reduce the latency sufficiently. In addition, this approach does not scale well. For example, consider a system with 10 camera modules running at 60 frames per second. This leaves 1/600 s = 1.7 ms per time slot. For there to be time to transmit data in this slot, the round trip latency, i.e., the time to transmit a packet from the Soft Hub and have data returned to the Soft Hub from the camera module must be better than 1.7 ms (Figure 6.2). This proved to be infeasible using the FTDI drivers and the PC hardware and software used to test this system.
n alternative approach that was successfully implemented uses a separate bus control
single wire connects each camera module using a general purpose I/O pin as
shown in Figure 6.3. The camera modules use this line to signal when they are using the bus and when they have finished. Each camera module is allocated a slot index. t first, time slot number zero is active and the module with slot index 0 sends its data. When the module begins using the bus it sets the bus control signal to a logic one. This alerts all other modules that the bus is busy. When finished the module’s timing signal port goes into a high impedance state that effectively disconnects the module from the bus control signal. The bus control line has a pull-down resistor attached that pulls the line down to a logic zero. The falling edge generates an interrupt in each camera module that is registered by a
counter in the module’s firmware. This counter tracks which slot is current.
t the completion of the time slot (on the falling edge) with index 0, the time slot number
1 becomes active and the module with this slot index takes control of the bus and asserts the bus control signal while it sends its data letting it fall when transmission is completed. The process continues until the last module on the bus has transmitted. t this point the process loops so that after the last time slot has been used time slot zero is active again.
This approach works well and is more scalable than the first system.
This is due to the