Principles of Top-Down Mixed-Signal Design
Traditional Approaches to Mixed-Signal Design
While the bottom-up design style continues to be effective for small designs, large designs expose several important problems in this approach.
Once the blocks are combined, simulation takes a long time and verification becomes difficult and perhaps impossible. The amount of verification must be reduced to meet time and compute constraints. Inadequate verification may cause projects to be delayed because of the need for extra silicon prototypes.
For complex designs, the greatest impact on the performance, cost and functionality is typically found at the architectural level. With a bottom-up design style, little if any architectural exploration is performed, and so these types of improvements are often missed.
Any errors or problems found when assembling the system are expensive to fix because they involve redesign of the blocks.
Communication between designers is critical, yet an informal and error prone approach to communication is employed. In order to assure the whole design works properly when the blocks are combined, the designers must be in close proximity and must communicate often. With the limited ability to verify the system, any fail- ure in communication could result in the need for additional silicon prototypes.
Several important and expensive steps in the bottom-up design process must be per- formed serially, which stretches the time required to complete the design. Examples include system-level verification and test development.
The number of designers than can be used effectively in a bottom-up design process is limited by the need for intensive communication between the designers and the inher- ently serial nature of several of the steps. The communication requirements also tend to require that designers be co-located.
Moving to Top-Down Design
In order to address these challenges, many design teams are either looking to, or else have already implemented, a top-down design methodology [1,5,7,19,21]. In a primitive top-down approach , the architecture of the chip is defined as a block diagram and simulated and optimized using a system simulator such as Matlab or Simulink. From the high-level simulation, requirements for the individual circuit blocks are derived. Cir- cuits are then designed individually to meet these specifications. Finally, the entire chip is laid out and verified against the original requirements.
This represents the widely held view of what top-down design is. And while this is a step towards top-down design, it only addresses one of the issues with bottom-up design (point 2 in Section 3.1). In essence, these design groups have not fundamentally changed their design process, they have simply added an architectural exploration step to the front. The flaw in this approach is that there is a important discontinuity in the design flow that results because the representation used during the architectural explora- tion phase is incompatible with the representation used during implementation. This dis- continuity creates two serious problems. First, it leaves the block designers without an efficient way of assuring that the blocks all work together as expected. One could assemble transistor-level representations of the blocks and run simulations, but the sim- ulations are too slow to be effective. The first time the blocks can be thoroughly tested together is first silicon, and at that point any errors found trigger a respin. Second, the discontinuity makes communications more difficult and ad hoc and so acts to separate
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