Principles of Top-Down Mixed-Signal Design
Principles of Top-Down Design
tem is represented largely at the transistor level. At this stage, the simulations are quite slow and the amount of functionality that can be verified is very limited.
In a well-conceived top-down design process a verification planning step occurs that focuses on anticipating and preventing the problems that occur when assembling the blocks into a system. In order to be effective, it must move the verification to as early in the design process as possible and occur with as much of the system described at a high level as possible. Moving the chip-level verification up in the design process means that errors are caught sooner, and so are easier and less expensive to fix. Using high-level models means that the simulations run faster, and so can be substantially more compre- hensive.
In a zealousness to accelerate the simulation, care must be taken to assure that enough of the system is at the right level to assure that the desired verification is actually occur- ring. Thus, the verification plans must include both simulation plans, that describe how the verification is to occur, and modeling plans, that indicate which models need to available to support the verification plan and which effects should be included in the models. The modeling plan is very important. Without it behavioral models may be written that do not include the desired effect while including many effects that are unre- lated to what is being verified. If they do not model the desired effect, then the verifica- tion will not be effective, if they model too many effects, then the verification runs unnecessarily slow and the models become more difficult and expensive to develop. The goal with the modeling plan is to identify a collection of simple models along with directions as to when they should be used, rather that trying to develop one complex model that is used in all cases.
An important benefit of the verification plan is that it allows the design team to react to late changes in the design requirements with confidence. When a change to the require- ments occur, it is possible to quickly revisit the verification plan, modify the design, update the models, and then apply it to the amended design to assure it satisfies the new requirements. Since it spells out all the simulations that need to occur to verify the design, there is little chance that a change needed by the new requirements that happens to break some other part of the design will go unnoticed.
Another important benefit of the up-front planning process used when developing the verification plan is that it tends to sensitize the design team to possible problem areas, with the result that those areas are less likely to become problems.
4.4 Multiple Passes
To reduce the risk of design iterations that result from unanticipated problems, it is important to take steps to expose potential problems early by working completely through an abstract representation of the design, using estimates as needed. As the design progresses and more detailed and reliable information becomes available, the abstract representation is successively refined. This process begins by developing a top- level behavioral model of the system, which is refined until it is believed to be an accu- rate estimate of the desired architecture. At this point, there should be reasonable under- standing as to how the blocks will be implemented, allowing size estimates to be made for the blocks, which leads to an initial floorplan. Top-level routing is then possible, which leads to parasitic extraction, with the effect of the parasitics being back annotated to the top-level. Simulations can then expose potential performance problems as a result of the layout, before the blocks are available. This may result in early changes to the
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