X hits on this document

PDF document

The Designer’s Guide Community - page 21 / 31





21 / 31

Roles and Responsibilities

Principles of Top-Down Mixed-Signal Design

cations on the individual blocks, and to develop the test plan. In addition, the team lead would work with the top-level designer on the power supply, bias and clock distribution.

6.2 Top-Level Designer

The top-level designer works on a single project at a time and is responsible for specify- ing how the various blocks that make up a design will be assembled. As such, he or she owns the floorplan, and the inter-block wiring and helps the system designer with the architecture. The top-level designer is responsible for the top-level verification and mixed-level simulation, and so owns the responsibility for developing the overall test bench. He or she also designs the power supply, bias and clock distribution network with help from the team lead, and optionally works on the overall architecture, specifi- cations, and test plan with the team lead, the system designer, and the architect.

The top-level designer owns the top-level schematic for the design. This schematic must be captured before any block design begins, even though it is likely to change before the design is complete. The top-level schematic specifies the partitioning of the design into blocks and the interface for each block. So each block should be “pin-accurate”. By this is it meant that in the top-level schematic, each block, and each pin on each block, is represented, and the type of each pin is carefully defined and documented. For example, an enable line on a block may be denoted “3V CMOS active high” or a trigger line may be described with “5V TTL positive edge triggered”. In this way, the top-level sche- matic provides clarity of intention to the design team. As the owner of the top-level schematic, the top-level designer must approve any changes to the interfaces of the blocks, and when changes occur must coordinate the updating and distribution of the new top-level schematic and models to the design team.

Most top-level simulation, especially in the final phase of the project, involves a lot of transistor-level simulations with extracted parasitics. For this reason the top-level designer is in general a different individual from the system designer. System designers tend to be more knowledgeable of architectures and algorithms. The top-level designer is in general an experienced block level designer that understands physical design very well, but he also has knowledge of the architecture. Top-level simulations can be very tricky. It is important that the top-level designer be facile with circuit simulators in order to overcome simulation problems and to obtain result in a reasonable time and with enough accuracy. These do not need to be run for every process corner but only for the one or two that are the most critical.

6.3 System Designer

The system designer tends to work on multiple projects simultaneously and is responsi- ble for the algorithm development, the architecture, and system-level simulation (using tools such as SPW, Matlab, Simulink, SystemView, Excel, Verilog, Verilog-AMS, soft- ware written ad-hoc, etc.). He or she also optionally works on partitioning of perfor- mance specifications to the various blocks and the test plan with the team lead, the top- level designer, and the architect.


Block Designers

The block designers tend to work on a single project at a time and are responsible for one or more block designs within that project. As such, they take care of all aspects of

The Designer’s Guide Community

21 of 31


Document info
Document views42
Page views42
Page last viewedFri Oct 21 22:13:56 UTC 2016