Mixed-Signal Hardware Description Languages
Principles of Top-Down Mixed-Signal Design
8 Mixed-Signal Hardware Description Languages
Both Verilog-AMS and VHDL-AMS have been defined and simulators that support these languages are emerging. These languages are expected to have a big impact on the design of mixed-signal systems because they provide a single language and a single simulator that are shared between analog, digital, and eventually system designers. It will be much easier to provide a single design flow that naturally supports analog, digi- tal and mixed-signal blocks, making it simpler for these designers to work together.
AMS languages make it substantially more straight-forward to write behavioral models for mixed-signal blocks, and they bring strong event-driven capabilities to analog simu- lation, allowing analog event-driven models to be written that perform with the speed and capacity inherited from the digital engines. This is very important, because most of the analog and mixed-signal models used in high-level simulations are naturally written using event-driven constructs. For example, blocks like ADCs, DACs, PLLs, ΣΔ con- verters, discrete-time filters (switched-capacitor), etc. are easily and very efficiently modeled using the analog event-driven features of the AMS languages.
Finally, is important to recognize that the AMS languages are primarily used for verifi- cation. Unlike the digital languages, the AMS languages will not be used for synthesis in the foreseeable future because the only synthesis that is available for analog circuits is very narrowly focused.
Verilog-A is an analog hardware description language patterned after Verilog-HDL . Verilog-AMS combines Verilog-HDL and Verilog-A into an MS-HDL that is a super-set of both seed languages . Verilog-HDL provides event-driven modeling constructs, and Verilog-A provides continuous-time modeling constructs. By combining Verilog- HDL and Verilog-A it becomes possible to easily write efficient mixed-signal behav- ioral models. A unique feature of Verilog-AMS is that it provides automatic interface element insertion so that analog and digital models can be directly interconnected even if their terminal / port types do not match. It also provides support for real-valued event- driven nets and for back-annotating interconnect parasitics.
AMS Designer, a commercial version of Verilog-AMS that also supports VHDL, is available from Cadence Design Systems .
VHDL-AMS [8,18] adds continuous time modeling constructs to the VHDL event- driven modeling language . Like Verilog-AMS, mixed-signal behavioral models can be directly written in VHDL-AMS. Unlike with Verilog, there is no analog-only subset.
VHDL-AMS inherits support for configurations and abstract data types from VHDL, which are very useful for top-down design. However, it also inherits the strongly typed nature of VHDL, which creates problems with mixed-signal designs. Within VHDL- AMS you are not allowed to directly interconnect digital and analog ports, and there is no support for automatic interface element insertion built-in to the language. In fact, you are not even allowed to directly connect ports from an abstract analog model (a signal flow port) to a port from a low-level analog model (a conservative port). This makes it
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