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Principles of Top-Down Mixed-Signal Design

Design Example

difficult to support mixed-level simulation. These deficiencies have to be overcome by a simulation environment, making VHDL-AMS much more dependent on its environ- ment. This should slow deployment of effective VHDL-AMS-based flows.

ADvance-MS, a commercial version of VHDL-AMS that also supports Verilog, is avail- able from Mentor Graphics [23].

9 Design Example

Recently a SONET OC-48 compliant serdes macro was designed by Cadence Design Systems. A serdes macro is an IP block intended to be instantiated on a large chip. Ser- des is short for serializer-deserializer. It is illustrated in Figure 2. It is an essential part of a high-speed serial link and includes the whole link interface. The figure shows a unidi- rectional link with a serializer at one end and a deserializer at the other. In addition, there is always a reverse link (not shown). As such, each end of the link requires both a serializer and a deserializer (a serdes).

FIGURE 2 An optical transceiver system.

Input

Framer

Serializer

Mux

D

Retimer FF

Q

Laser Driver

÷N

Frequency

Power

Synthesizer

Control

Transmitter

Fiber

TIA

Limiter

Deserializer Decision Ckt

FF DQ

DMux

Deframer

Output

AGC

Clock Recovery

÷N

Receiver

The deserializer is the more challenging of the two halves of a serdes, as it requires clock recovery. To get the highest data rate serial links use a non-return to zero (NRZ) coding in which the bit value is kept constant for the whole clock cycle. The NRZ cod- ing produces a signal spectrum that contains little energy at the actual clock frequency, and so a clock recovery circuit is needed. It is typically a specialized type of phase- locked loop (PLL). When multiple serdes reside on the same chip, the voltage-con- trolled oscillators (VCO) found in most PLLs (see Figure 3) can inadvertently interact

26 of 31

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