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Design Example

Principles of Top-Down Mixed-Signal Design

with each other. Coupling that occurs between the oscillators can cause one to injection lock to another, which would result in a failure to recover the clock. Cadence avoided this problem by using a single reference oscillator, and by replacing the VCO in each PLL with a phase interpolator fed by the reference oscillator as shown in Figure 4.

FIGURE 3

Conventional clock and data recovery.

Clock and Data Recovery

Data In

D

Decision

Q

Data Out

Clock Recovery

Phase Detector

Loop Filter

VCO

Clock Out

FIGURE 4

Clock and data recovery using reference oscillator and phase interpolator.

Clock and Data Recovery

Data In

D

Decision

Q

Data Out

Phase

Loop Filter

Phase

Detector

Interpolator

Clock Recovery

Reference Clock

Clock Out

The design occurred before the design group adopted an AMS simulator, but given the largely digital nature of the circuit, they were able to use Verilog to support a mixed-sig- nal top-down design process. After an initial algorithm exploration phase using models written in a general programming language, the architectural design phase commenced by writing Verilog models for every cell. The high-level architectural model was used to verify correct operation in each of the over 100 operating modes of the serdes. The main concern of the designers centered around the charge pump and phase interpolator, so a verification plan was developed that used mixed-level simulation to extensively verify the clock recovery circuit with these blocks at the transistor level. Designers were more comfortable with the purely digital components such as the phase detector and the divider, and so traditional cell characterization was used to develop bottom-up models that were included in most of the simulations. Mixed-level simulations were performed over a combination of nearly 100 corner cases in terms of process parameters, tempera- ture, and supply voltage to assure reliable operation of the phase interpolator. Each sim-

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