Principles of Top-Down Mixed-Signal Design
over several thousands of cycles, an average growth rate of 10× per decade. Examples include PLLs, ΣΔ converters, magnetic storage PRML channels, and CDMA transceiv- ers. The result of these two effects together is that verification complexity is increasing at a blistering pace or roughly 300× per decade, and is outstripping the designers ability to keep up.
The CAD tools and computers employed by designers continually improve, which serves to increase the productivity of designers. However, the rate of productivity increase is not sufficient to allow the designers to keep up with the increasing complex- ity of designs and decreasing time-to-market requirements. The growing difference between the improvement in productivity needed to satisfy the demands of the market and the productivity available simply by using the latest CAD tools and computers is referred to as the design productivity gap. To close this gap, one must change the way design is done. As Dr. Henry Samueli, co-chairman and CTO of Broadcom, said at ISSCC ’99, “Fundamental improvements in design methodology and CAD tools will be required to manage the overwhelming design and verification complexity” . A design style that reduces the number of serial steps, increases the likelihood of first time working silicon, and increases the number of designers that can work together effec- tively is needed.
2.3 Avoidance of Risk
The recent downturn in the economy has exposed additional issues with the existing analog design process. With a tight economy, a long time-to-market is not the only rea- son why a good product might fail to exploit an available opportunity. It is also very important that the design make it to production with very few respins (and those respin should only involve changes to the metal mask), otherwise the opportunity might be lost due to a limited development budget. Budget limitations are exacerbated by the high cost of CMOS IC fabrication, and these costs are expected to grow rapidly, making respins increasingly problematic in the future. This is a particular problem for analog and mixed-signal design. For the same market value, mixed-signal design requires more resources, more talent, more design time, and hence, a larger development budget than digital design. The need for respins also injects substantial uncertainty into the planning process, which acts to increase the risk of designs that involve analog circuitry.
In uncertain economic times companies are much less likely to take on high-risk analog projects. Nor are they likely to add substantial risk to large digital designs by adding analog or mixed-signal circuitry. Rather, mixed-signal systems will be partitioned to the degree possible so that the analog circuitry is placed on a separate chip from the digital circuitry. Such a partitioning may be non-optimal in terms of power consumption and performance, but is deemed necessary to achieve acceptable levels of risk and cost. Once a working analog or mixed-signal chip is achieved, it will tend to be used repeat- edly without change in successive versions of the system. Redesigning the analog por- tion of the system may result in lower system costs and improvements in performance, but simply takes too long and involves too much risk.
A more error prone design process also affects analog and mixed-signal design in another way. The errors that are common place in the early versions of mixed signal designs are often very difficult to track down. For this reason, mixed-signal designs often include additional circuitry that is used to help find these problems. This addi-
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