JANUARY 2005 / 5
company has bumped out its unveil- ing date by several months.
Howard Sachs, President & CEO (Pre- viously held management positions with Fujitsu Microelectronics, Inter- graph, Fairchild and Cray. He was the president of the Virtual Socket Industry (VSI) Alliance and VP of technologies at Fujitsu responsible for EDA methodologies)
Richard Dickson, VP of R&D (previ- ously worked with Sachs at Fujitsu Microelectronics, Intergraph and Cray)
Michael Barry, Ph.D., VP of Opera- tions (previously held senior man- agement positions at Fairchild R&D, Vitelic, Intergraph and Peri- com)
Shubha Tuljapurkar, VP of Marketing & Sales (previously held senior management positions at Intel, LSI Logic and Mosel Vitelic as well as serving as VP and GM at Silicon Magic)
3375 Scott Blvd., Suite 300 Santa Clara, CA 95054 Tel: 408.764.0270 Fax: 408.764.0271 www.telairity.com
Teradici was formed in Q4 2003 to develop semiconductor solutions for next-generation personal computers, tablets and handhelds. “Through a combination of unique algorithms and high-performance silicon processing, the company is focused on enabling a new approach for how personal com- puters are deployed and managed.” The company has secured US$8.3 million ($10.2 million Canadian) in initial fi- nancing led by GrowthWorks Capital, manager of the Working Opportunity Fund, and syndicated with the Busi- ness Development Bank of Canada (BDC) and Skypoint Capital. In Janu-
ary 2005, Teradici may seek an addi- tional $2 million. The company has 10 employees.
Dan Cordingley, President and CEO (previously held general manage- ment roles at Intel and Level One)
Maher Fahmi, VP of Silicon Engineer- ing (previously Director of Product Development for service provider products at PMC-Sierra)
Ken Unger, VP of Software Engineer- ing (previously Director of Engi- neering for VoIP products at Broadcom)
David Hobbs, Chief Architect (previ- ously VP of Engineering and CTO for Spectrum Signal Processing)
Sam Davison, VP of Finance (previ- ously Controller for Broadcom’s CarrierAccess and Mobile Commu- nications business units)
#500, 4400 Dominion Street Burnaby, BC V5G 4G3 Canada Tel: 604.628.1201 Fax: 604.451.5818 www.teradici.com
CommASIC was founded in March 2001 as a systems design consultancy for global communications manufac- turers in wireless designs. During this time CommASIC developed a propri- etary architecture for power efficient multimodal wireless baseband pro- cessing. In 2003, CommASIC pro- gressed into a product development organization. CommASIC’s mission is now “to become the dominant provid- er of baseband technology for wireless multimode broadband terminals, in- cluding portable and mobile devices such as cellphones.”
In September 2004, CommASIC se- cured $10 million in Series A funding
from private investors and VCs from Asia (Ho Tung Group, Chiao Tung Bank, TSCVentures and Fortune Tech Ventures). Additional capital require- ments are anticipated in mid-2005. The company has roughly 30 employees and is headquartered in San Diego, CA, with a subsidiary in Taiwan.
Today, most baseband devices are ei- ther DSP-based or ASIC-based. How- ever, each approach has its limitations. As an example, multimode is only available in ASICs with significant overhead in complexity and gate count. ASICS are risky, lack scalability and flexibility and require costly respins to add new features. Meanwhile, DSPs may not be suitable for very high rate designs because of their speed and MIPS limitations, and tend to be area inefficient and power hungry.
CommASIC has developed the Wire- less Broadband Signal Processor (WBSP) Architecture to enable multi- mode broadband networking in porta- ble devices with power efficiency, performance, programmability and die size unmatched by any other conven- tional ASIC or DSP technology.
The WBSP Architecture is neither a software-defined radio nor a re-config- urable DSP, rather a communications engine built using traditional ASIC blocks, yet with efficiency and perfor- mance superior to a conventionalASIC architecture. Solutions based on the WBSP architecture reduce baseband circuitry and improveASIC algorithms to achieve ultra low power consump- tion, gate count and silicon cost.
The processing core of the WBSP can be programmed to perform virtually any algorithm and support any wire- less standard. In the WBSP, there is no dedicated control path (i.e., both data and control share the same path), thus reducing complexity and gate count. The WBSP elements can be reconfig-
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