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6 / JANUARY 2005

SEMICONDUCTOR TIMES

Startup Profiles

(Continued from page 5)

ured to perform different tasks, which reduces the number of processing ele- ments and consequently the gate count. For an 802.11a/b/g modem, the LP1070 has 120k gates for the modem (excluding memory and microproces- sor), which is claimed to be far less than the industry average, which exceeds 400k gates, according to the company.

The WBSP can dynamically configure itself based on the current frame being processed. This dynamic processing manifests itself in two forms:

1. Reduced Operation Count –The WBSP always performs the “right amount” of processing on each frame, based on the frame’s SNR or signal quality, which lowers the number of operations performed on the received data, on average.

2. Variable Bit Widths – WBSP has the ability to dynamically alter its bus widths for the processing units being operational.

Furthermore, unlike conventional ASICs, in the WBSP, modules are only

clocked when they operate. WBSP modules, when clocked, produce a use- ful output at every clock cycle, never wasting a clock cycle. The internal ARM processor only runs when nec- essary for MAC-layer processing.

As an example, the same WCDMA handset which typically operates for 2 hours of talk time using competing baseband solutions will operate for 10 hours of talk time using CommASIC’s solution. And the same DVB-T porta- ble video device which typically op- erates for 2 hours based on traditional ASIC will operate for more than 20 hours using the CommASIC WBSP architecture.

The WBSP Architecture was designed to support multiple wireless broadband communication technologies such as 802.11a/g at 54Mbps, W-CDMA and WiMAX, and will serve as the migra- tion path to newer, evolving high- speed wireless standards and next-generation spectrum-capacity enhancing techniques such as Multi- ple-Input-Multiple-Output (MIMO) and Multi-User-Detection (MUD).

Based on the multimode WBSP archi- tecture, CommASIC recently intro-

duced its first two products, the LP1071 and LP1072 802.11a/b/g base- band processors, which combine the industry’s lowest power consumption, according to the company, with DSP- like flexibility. The chips are specifi- cally designed for power and cost sensitive portable consumer devices such as VOIP handsets, wireless PDAs and digital cameras.

The LP1071 and LP1072 employ a sin- gle common hardware engine to sup- port multiple communication modes – 802.11 b CCK and 802.11a/g OFDM. Based on the WBSP platform, the de- vices can be “programmed” for opti- mum power/performance, unlike conventional fixed-pipelined ASICs.

The LP1071, at 9x9x1.0 mm, supports SDIO host interface and is claimed to be the smallest integrated 802.11a/b/g MAC/BB package available. The LP1072 baseband processor supports both SDIO and CF+ host interfaces, and also provides additional GPIO’s and SRAM-to-host interfaces for in- crease performance. Both products ful- ly embed upper and lower MAC functionality inside the chip, which is essential when adding WLAN capabil- ity into applications such as mobile phones and consumer electronics.

The devices integrate ADC, DAC and internal memory to reduce the BOM and overall system cost. To provide support for real time applications with QoS requirements, the devices support the 802.11e draft standard. Hardware engines for WEP, TKIP and AES re- duce processor load. The devices sup- port Direct Conversion (Zero-IF) radio architectures, and include support for Maxim and Airoha front-ends.

CommASIC claims that the LP1071 and LP1072 802.11 chips use just one- eighth the active power of competing products and only 1/20th the standby power of others. The processors draw

Copyright Pinestream Communications, Inc. 52 Pine Street, Weston, Massachusetts 02493 USA Tel 781.647.8800 Fax 781.647.8825 www.pinestream.com info@pinestream.com

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