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EIA IBIS Open Forum Summit Minutes - page 4 / 13





4 / 13


Eckhard Lenski, Nokia Siemens Networks, Germany

Eckhard started with a short review about pre-/de-emphasis.  He explained that despite the two logic states for high and low, there might be four states.  These can be defined from pre-/de-emphasis settings as “low”, “low-pre”, “high” and “high-pre”.  He showed that four different switching modes can be defined that correspond to the last logic state prior to the switching.

He continued with some remarks about the availability of information on [Driver Schedule] modeling, which can be found either in a lot of IBIS summit presentations, in the IBIS Cookbook 4.0 and IBIS Version 4.2.  He showed that is very important to know which static curves of which model are used in the [Driver Schedule].  These are the [POWER Clamp] and [GND clamp] curves from the top level model and the [Pullup] and [Pulldown] curves from the scheduled models.  He than compared a data signal with a clock signal, with the important parameter of UI (Unit Interval) for a data signal and the clock period for a clock signal.  He said that from the UI, it is very simple to calculate the data rate, by calculating the reciprocal. He pointed out that for a data pattern that is composed of alternating 1s and 0s, a maximum corresponding frequency of the data rate can be calculated as F =  (Data rate / 2).

He then explained that, for a classical IBIS model, a max frequency where the model can be used at is calculated out of the rising and falling times of the waveforms by:

Fmax = 1 / ( trise + tfall ).  By using a [Driver Schedule] for SerDes multi-gigabit applications, this is no longer true, as now it has to be taken into account that a signal has to be long enough above the high-threshold or below the low-threshold, which results in an eye diagram.

He then showed the influences of using a normal push-pull CMOS model at increasing frequencies, which end up that the model looks suspicious when the frequency is greater than Fmax = 1 /( trise + tfall ).  From the signal characteristics of a model with pre-emphasis, it can be seen that both the rising and the falling edges contain information for two bits or two UI.  The first bit shows the emphasized behavior of the output, while the second bit shows the behavior without pre-emphasis.

Five examples were shown of using a [Driver Schedule] model at different clock frequencies. For 250MHZ and 500MHz both the logic state with and without emphasis can be seen.  At a frequency of 1000MHz, the signal just shows a switching from high-pre to low-pre. All five examples showed that the use of a [Driver Schedule] model in n ‘clocking or frequency’ application is not valid. So therefore the use a PRBS (pseudo random bit sequence) is necessary, to really show all possible switching modes of the model containing pre-emphasis. Eckhard continued with 4 examples that used different UI to show a realistic behavior. He said that only by using the correct UI in the simulation, which is the same UI that is encoded in the model, a correct switching and/or eye diagram could be measured.

In his summary he pointed out that normal push-pull CMOS models can be used up to a specific frequency Fmax, but a [Driver Schedule] modeling pre-emphasis can only be used for one data rate.  The reason for this is that in this [Driver Schedule] model a data pattern of 1100 is encoded in the model behavior which will only be valid for the corresponding UI or data rate (in comparison to the push-pull CMOS model, which only has the classical 10 pattern encoded).  He closed with the remarks that the user himself has to take care of using the correct data rate, as the tool doesn’t care about the UI or encoded pattern of the model.

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