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EIA IBIS Open Forum Summit Minutes - page 7 / 13





7 / 13


Sam Chitwood, Sigrity, USA (Presented by Brad Brim, Sigrity, USA)

Brad pointed out that IBIS is a well-established standard, and therefore it helps a lot to define how an IBIS model should look and which information it should contain. But he also pointed out that as with many things, there are some limitations which should be overcome.  This is especially true for power integrity analysis, where a lot of improvements are needed.

He explained that in IBIS there is an assumption of a 1:1 relationship between the die pads and the board pins.  He figured out that this is true for lead frame packages, but for modern BGA packages, there are power planes inside the package and not only pads.  [Pin Mapping] is a first step in the right direction, but he remarked that these connections with the current IBIS standard are ideal and no die parasitics are taken into account.

He continued with the [Pin] list keyword.  In this list all pins should be included, but very often the power and ground pins are omitted.  What is missing here is that there is no coupling modeled between the pins.  There are some limitations for the [Pin] parameters for PDS simulations, e.g. there are no mutual values, and therefore no current loops can be defined. Furthermore, for high frequency, both power and ground pins have to be assumed as RF ground.  For using the [Pin] list in signal modeling, there are three problems: C_pin should be divided in C_pin-PWR and C_pin-GND like it is done with C_comp; for inductance there is no mutual inductance, so it is difficult to define a current return path; the parameter R-pin has no frequency dependency, so one does not know if the skin effect is included or not.

Brad continued with hints for proper extraction of [Pin] inductance, resistance and capacitance, but noted that you still have to keep in mind that these values should only be used for an ideal PDS simulation.  So, for all measurements, the power and ground pins should be AC-shorted, by doing so, the inductance will become L_loop, including mutual inductance, and capacitance will become C_total, including C_pwr-signal, C_gnd-signal and C_sig-signal.

For the values in the [Package] section he explained, that very often in the min and max columns, there is a mixture of signal pin values and power pin values.  This results in values of L_pkg which are too small and C_pkg which are too big (summation of parallel C’s and parallel L’s in power pins).

Advanced packaging features may be used through the [Define Package Model], which itself can be separated in two types.  One is the [Number of Sections], which has the same drawbacks as the [Pin] parameters.  The second is [Model Data], which is a real improvement, because you can model coupling between pins.  He continued with a suggestion for the extraction of the parameters, where for better results all corresponding power pins and ground pins should be lumped together as positive or negative references respectively. It is important that now there would be just one pin listed for the power pins, and the ground pin would not even be listed.  He showed a picture which showed that the performance of an IBIS RLC model could be improved by using a broadband approach of using frequency dependant matrices. He ended his presentation with remarks of not using on-die de-caps in the package models, as this will cause resonance-problems, and that only the pins which do have de-caps should be mentioned.

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