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EIA IBIS Open Forum Summit Minutes - page 8 / 13





8 / 13


Flavio Canavero, Ivan Maio, and Igor Stievano, Politecnio di Torino, Italy

Igor started his presentation with the information that there are real parts like stacked SiP devices that show a power variation in VCC of about 30-40% from the nominal value. This is far beyond the approach of BIRD 98.1, which will cover variation of approximately 10-15%.

He continued by showing that this problem is common to all kinds of behavioral models like IBIS, Mπlog, etc.  He gave an overview of the structure of the Mπlog model and explained that all the necessary parameters have been computed for the nominal power supply.  Two errors for the model behavior were shown when using large power supply variations. The first is a static error, which showed up in different voltage values for the output behavior.  The second error could be identified as a timing error, because the overall behavior showed a delay compared to the reference.

One choice to improve the model would be to extract all the different static curves for each corresponding VCC value, but this might be too time consuming.  So he thought about reducing this by looking at the actual operating range of the device.  He found that around the load-curves with 50 ohms to VCC and 50 ohms to ground a region could be found where a device is normally operated. By including this information (operation around the load lines) in the Mπlog model, the static errors disappeared.

This was done by matching the correcting factor kL(vdd) to analytical NMOS equations.  Igor pointed out that this region is also valid for using the model under pure capacitive load conditions.  His next slide showed that the dc-errors had disappeared, but the dynamic errors still were there.  So now this delay had to be modeled. He showed that in standard books there exist equations which describe the delay propagation in accordance to VCC fluctuations with an accuracy of approximately 5%.   After adding this corrective factor to the new Mπlog model, the dynamic error disappeared.

A comparison between the old and the enhanced Mπlog model was shown. He pointed out that the main advantage of this method is that no additional characterization is required.  So just by enhancing the nominal Mπlog model with the two correction factors for VDD variation, one can deliver models which include the behavior for large VDD variations.  These enhanced models are still very accurate.

A question was asked for which classes of circuits this approach is valid.  Igor answered that it is valid for classical devices which have a digital output, but also for differential outputs and even for precomps.   For precomps one has to take into account that the modeling must be done in a different way, because the rule/equation for the deviation of VDD is greater than 5%, so the delay error has to be modeled differently.  Igor pointed out that even the mentioned stacked SiP could be modeled correctly.

Someone asked if this approach would work for non-linear parts.  Igor pointed out that the part had to be separated into a kind of sub system level with core, IO and supply considerations.  The nonlinear part will be either extracted from simulation or has to be measured, but the package has not been under investigation.

The last question was about the validity of this load lines approach.  Igor explained that in a

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