HDCP Specification v1.1 Amendment for HDCP-GVIF Revision 1.0
Authentication protocol is an exchange between an HDCP-GVIF transmitter and an HDCP-GVIF receiver to ensure the HDCP-GVIF receiver is authorized to receive HDCP content. In case of HDCP-GVIF, HDCP-GVIF channel embedded communication is used for the exchanges instead of I2C bus.
HDCP specifies operation mode of DVI mode and HDMI mode, whereas GVIF-HDCP has only GVIF mode. In the state diagrams (for transmitter, receiver and repeater), HDCP-GVIF shall transit to HDMI mode state when state diagram is divided into DVI mode or HDMI mode. Hence, Bit field 12 of B-status register is always set to 1.
2.2.2 EDID ROM Reading HDCP-GVIF does not support EDID ROM reading. GVIF-HDCP devices pass over the Read EDID state in the state diagram. EDID ROM Reading is subject to be considered to support in future modification.
2.2.3 Hot Plug Detect (HPD) Since HDCP-GVIF embed the exchange communication onto HDCP-GVIF channel, authentication protocol shall not start until bit clock synchronization between HDCP-GVIF transmitter and HDCP-GVIF receiver is established. In order to establish bit clock synchronization, at least pixel clock, VSYNC and HSYNC shall be supplied to HDCP-GVIF transmitter at anytime when HPD is detected or when HDCP-GVIF transmitter is active.
2.2.4 Receiver Lock Detect (RLD) Receiver Lock Detect is asserted when initialization state machine in GVIF transmitter indicates GVIF receiver synchronized to upstream GVIF transmitter. After RLD is asserted, GVIF transmitter can start the authentication protocol by request from upstream content control system.
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