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Design and implementation of the operation and maintenance software for a new GSM transcoder - page 13 / 26

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© NOKIA13 paavo.markkola@nokia.com18.10.2005

Implementation, Hardware Changes

Host processor is different Intel 80186EB @ 16 MHz AMD Am186ER @ 50 MHz

Instruction set is the same

Boot procedure is different

Boots from flash instead of ROM as in TCSM2

Must also copy itself from flash to RAM execution continues from RAM

Submultiplexer implemented with a Field Programmable Gate Array (FPGA) device

Needs to be loaded and configured

Storage flash memory is different

Size increased from 512 kB to 8 MB, but bank size decreased from 256 kB to 64 kB

DSP code loading memory is used to load DSPs

Banked to 64 kB pages with total size 512 kB

The DSP block and the interface to it are completely different

Use of High-Level Data Link Control (HDLC) channels to external devices (ET and clock units) depends on the location of the TR3E/A plug-in unit

Units have different roles  

Internal clock replaced with cabinet level external clocks

Only cabinet head master can control external clocks

Exchange terminals have 16 units instead of just two

Only cartridge master (Ater and A interface) and masters (A interface) have control over exchange terminals

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