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September 1999 P/N 880-503284-001-A1 - page 39 / 65

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NCC 2020 TAC 2010

Selects DSX-1 Equipment cable length of 399-532 ft.

NCC 2020 TAC 2010

Selects DSX-1 Equipment cable length of 533-655 ft.

NCC 2020 TAC 2010

Sets data bus to NONE (CSU mode) [default].

NCC 2020 TAC 2010 DIU 2140

Sets data bus to A (Mux mode).

NCC 2020 TAC 2010 DIU 2140

Sets data bus to B (Mux mode).

NCC 2020 TAC 2010 DIU 2140

Sets data bus to C (Mux mode).

NCC 2020 TAC2010 TAC 2130

Sends in-band CSU loop-up code to far-end CSU, this should cause the far end CSU to enter a Line Loopback condition.

NCC 2020 TAC 2010 TAC 2130

Sends framed QRSS to far end.

NCC 2020 TAC 2010 TAC 2130

Stops QRSS pattern and send inband CSU loop-down code to far end.

DIU 2140

Uses timeslot 24 on the assigned CSU. Sets all 5 data ports to 9.6 kbit/s.

DIU 2140

Selects split timing (RX clock ~ TX clock); typical value.

DIU 2140

Selects single source timing (RX clock = TX clock).

DIU 2140

Sets DTE timing option for all synchronous data ports to ST.

DIU 2140

Sets DTE timing option for all synchronous data ports to ST.

DIU 2140

Sets DTE timing option for all synchronous data ports to TT.

DIU 2140

Sets RTS to normal operation. For synchronous data ports, data is transmitted ONLY if the DTE asserts RTS (ignored in Async) [default].

DIU 2140

Sets RTS to forced on (requires version 1.1 DIU 2140 firmware), data is sent regardless of actual state of RTS from DTE. This behavior always applies to Async ports.

DIU 2130 TAC 2130

Sets Data Port 1 to tail-circuit timing. Note that TAC 2130-T and TAC 2130-S modules do not support tail circuit timing, external timing or TIU 2850 timing.

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Description

Configuration

Verilink NCC 2020 User Manual

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